A 25 GHz Analog Multiplexer for a 50GS/s D/A-Conversion System in InP DHBT Technology

2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2011-11-01 DOI:10.1109/CSICS.2011.6062440

D. Ferenci, M. Grozing, M. Berroth

引用次数: 16

Abstract

An analog 2:1 multiplexer for high speed analog multiplexing is presented in InP DHBT technology. The multiplexer features a SNDR above 26 dB with a differential input voltage of 1V-PP and a 3 dB corner frequency above 40GHz. The power consumption of the multiplexer is 1.35W at a supply voltage of 5.5V. The multiplexer is suitable for the realization of a 50GS/s digital-to-analog conversion system, which is more than two times faster than currently available fully sampling rate flexible D/A-conversion systems.

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基于InP DHBT技术的50GS/s数模转换系统的25ghz模拟多路复用器

提出了一种基于InP DHBT技术的模拟2:1多路复用器，用于高速模拟多路复用。该多路复用器SNDR大于26 dB，差分输入电压为1V-PP，转角频率为3db，高于40GHz。在5.5V电源电压下，复用器的功耗为1.35W。该多路复用器适用于实现50GS/s数模转换系统，比目前可用的全采样率柔性数模转换系统快2倍以上。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)

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