Two efficient area reduction methods for implementations of the Rijndael advanced encryption standard

The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI:10.1109/APCCAS.2004.1412768

Shen-Fu Hsiao, Ming-Chih Chen

引用次数: 1

Abstract

In this paper, we propose two methods to reduce the area cost of AES chip. The first method combines the SubBytes(), ShiftRows() and MixColumns() transformations in the cipher process, and the InvMixColumns(), InvShiftRows() and InvSubBytes() in the decipher process through the bit-level substitution and minimization. The second method integrates the combined SubBytes()/ShiftRows()/MixColumns() with the InvMixColumns()/InvShiftRows()/InvSubBytes() into a single function unit by sharing the common operations. Experimental results show that our design saves 21 % area cost of the entire AES chip

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实现Rijndael高级加密标准的两种有效的面积缩减方法

本文提出了两种降低AES芯片面积成本的方法。第一种方法结合了密码过程中的SubBytes()， ShiftRows()和MixColumns()转换，以及解密过程中的InvMixColumns()， InvShiftRows()和InvSubBytes()，通过位级替换和最小化。第二种方法通过共享公共操作，将组合的SubBytes()/ShiftRows()/MixColumns()与InvMixColumns()/InvShiftRows()/InvSubBytes()集成为单个函数单元。实验结果表明，我们的设计节省了整个AES芯片21%的面积成本

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.

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