High performance visibility testing with screen segmentation

Abstract

There are two factors determining the performance a 3D accelerator can achieve: the available computational power and the available memory bandwidth. In embedded systems, these resources are even more limited then in desktop environments, thus the efficiency of the hardware architecture and the exploitation of the logic resources become even more important. Most resources are wasted at the visibility testing process: traditional implementations require a lot of bandwidth, and process pixels which are not visible on the final image. By segmenting the screen, the presented architecture can use high performance, on-chip buffers to lower memory requirements and to provide high performance. The order of the processing guarantees that only those colors are computed, which are truly visible. The modular architecture allows satisfying different requirements: a trade off can be made between the number of processing units and performance.