Reliability of Strain-Si FPGA Product Fabricated by Novel Ultimate Spacer Process

Abstract

Strain-Si field-programmable gate arrays (FPGA) is fabricated by using ultimate spacer process (USP) with a single capping stress liner. An overall 15% speed enhancement without compromising yield was obtained. The product reliability assessment, including HTOL, TCT, ESD (CDM and HBM) and latch-up, was performed simultaneously on USP and control parts. They show comparable product reliability and both pass product specs. Wafer level device reliability was also studied for NBTI, HCI and oxide TDDB. Wafer level NBTI is well correlated with product level HTOL degradation. It is confirmed that USP technology improves product performance significantly, and the product reliability is comparable to that of baseline technology