Reducing power consumption of CMOS VLSI's through V/sub DD/ and V/sub TH/ control

Abstract

Lowering operating voltage, V/sub DD/, is a key to low-power CMOS digital VLSIs. In order to complete a certain task in a required time and in order to keep leakage current within a tolerable level in the low V/sub DD/ designs, V/sub DD/ and V/sub TH/ control is obligatory. This paper covers several of the schemes including multi-V/sub TH/, variable V/sub TH/, multi-V/sub DD/ and variable V/sub DD/ to achieve low-power systems. Circuit level ideas for software related research are described.