A high-accuracy, low-power consumption switched-capacitor interface of differential capacitance transducers

Abstract

A high-accuracy and low-power consumption interface of differential capacitance transducer based on switched-capacitor (SC) sample/hold (S/H) circuit including a fully-differential subtractor is presented. This interface reduces the nonlinear error by means of double sampling and does not require component matching. Performances of the proposed interface are simulated by HSPICE using a 0.35µm n-well CMOS process parameter. The results have demonstrated that the proposed interface offers increased linearity and lower power consumption.