J. Moreno, J. Madrenas, J. Cabestany, E. Cantó, R. Kiełbik, J. Faura, J. Insenser
{"title":"Realization of self-repairing and evolvable hardware structures by means of implicit self-configuration","authors":"J. Moreno, J. Madrenas, J. Cabestany, E. Cantó, R. Kiełbik, J. Faura, J. Insenser","doi":"10.1109/EH.1999.785451","DOIUrl":null,"url":null,"abstract":"In this paper we shall address the physical implementation of self-repairing and evolvable hardware strategies. These alternatives will be enabled by the specific dynamic reconfiguration capabilities included in a new family of FPGA devices, called FIPSOC (Field programmable System On a Chip). The main features of these devices are given by the integration on a single chip of a dynamically reconfigurable FPGA, a programmable analog section and a microcontroller. As our experimental results will show, the efficient use of the available resources makes these devices an excellent platform for testing, developing and realizing physically new concepts in electronic design.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EH.1999.785451","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
In this paper we shall address the physical implementation of self-repairing and evolvable hardware strategies. These alternatives will be enabled by the specific dynamic reconfiguration capabilities included in a new family of FPGA devices, called FIPSOC (Field programmable System On a Chip). The main features of these devices are given by the integration on a single chip of a dynamically reconfigurable FPGA, a programmable analog section and a microcontroller. As our experimental results will show, the efficient use of the available resources makes these devices an excellent platform for testing, developing and realizing physically new concepts in electronic design.