A micropower EEG detection system applicable for paralyzed hand artifical control

Aisha A. Alhammadi, Maha S. Diab, S. Mahmoud
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引用次数: 6

Abstract

In this paper, Analog Front-End EEG system is designed. It consists of cascaded instrumentation amplifier (CIA), dual-notch low-pass filter (DNLPF), and programmable gain amplifier (PGA). The proposed CIA is voltage amplifier based on gyrator realized by two digitally programmable operational transconductance amplifiers (DPOTAs). It achieves 31dB gain besides providing high-pass feature. To minimize the effect of powerline interference, DNLPF is designed. Furthermore, it has low-pass feature to attenuate unwanted noise signal, and this offers compactness in term of chip area. PGA fortifies processed EEG signal with more gain. Its structure is built from master/slave paths to achieve high linearity. PSpice simulation results are carried out using 0.25-μm CMOS process and operating under ±0.8V. Simulation results for EEG system achieve controllable gain (61dB–84dB), input referred noise of 4μV/√Hz, and power dissipation of 32μW. As an EEG-oriented application, brain-computer interface (BCI) system is proposed to be used in paralyzed limb artificial control.
一种适用于瘫痪手人工控制的微功率脑电图检测系统
本文设计了模拟前端脑电系统。它由级联仪表放大器(CIA)、双陷波低通滤波器(DNLPF)和可编程增益放大器(PGA)组成。所提出的CIA是由两个数字可编程运算跨导放大器(DPOTAs)实现的基于陀螺的电压放大器。除提供高通特性外,还可实现31dB增益。为了减小电力线干扰的影响,设计了DNLPF。此外,它具有低通特性,以衰减不需要的噪声信号,这提供了紧凑的芯片面积方面。PGA对处理后的脑电信号进行增益强化。其结构由主/从路径构建,以实现高线性度。PSpice仿真结果采用0.25-μm CMOS工艺,工作电压为±0.8V。仿真结果表明,EEG系统实现增益可控(61dB-84dB),输入参考噪声为4μV/√Hz,功耗为32μW。脑机接口(BCI)系统作为一种面向脑电图的应用,被提出用于瘫痪肢体的人工控制。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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