Writing area-efficient hardware descriptions for logic synthesis

Abstract

Several advantages for using a hardware description language for logic synthesis are given along with some example programs. Variations in writing style are shown to have a significant effect on the optimization process used by the synthesizer since one style generally results in a physical layout that consumes only half that of another. Based on these experiences, a structured, object-oriented style that separates control and operations is recommended for the writing of area-efficient hardware descriptions.<>