ASIC design of digital ECG filter

Abstract

An ASIC (application-specific integrated circuit) design for a linear-phase ECG (electrocardiogram) filter is presented. The filter utilizes a novel recursive multiplierless architecture. A bit-serial approach has been chosen to keep circuit area and power consumption as small as possible. The implementation has been done using partly full custom and partly standard cell techniques, yielding high transistor density and gate array design efficiency. In the implementation module generators have been used to allow flexible altering of the filter structure.<>