S. Kapoulea, C. Psychalinos, J. Baranowski, W. Bauer
{"title":"CCII Based Realization of Fractional-Order PD Controller for a Position Servo","authors":"S. Kapoulea, C. Psychalinos, J. Baranowski, W. Bauer","doi":"10.1109/TSP.2019.8768878","DOIUrl":null,"url":null,"abstract":"A fractional-order proportional-derivative (PD) controller implementation for a position servo system is presented in this paper. The main offered attractive benefit is the employment of only one second-generation current conveyor (CCII) as active element, minimizing the active component count in comparison to the conventional way of implementation where three CCIIs are required for this purpose. The behavior of the controller is evaluated using the Cadence software and MOS transistor models provided by the $0.35\\mu m$ Austria Mikro Systeme CMOS process.","PeriodicalId":399087,"journal":{"name":"2019 42nd International Conference on Telecommunications and Signal Processing (TSP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 42nd International Conference on Telecommunications and Signal Processing (TSP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TSP.2019.8768878","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A fractional-order proportional-derivative (PD) controller implementation for a position servo system is presented in this paper. The main offered attractive benefit is the employment of only one second-generation current conveyor (CCII) as active element, minimizing the active component count in comparison to the conventional way of implementation where three CCIIs are required for this purpose. The behavior of the controller is evaluated using the Cadence software and MOS transistor models provided by the $0.35\mu m$ Austria Mikro Systeme CMOS process.