Comparative Analysis of Power Consumption of Parallel Prefix Adders

Abstract

This paper presents results and conclusions derived from simulations of tens structures of Parallel Prefix Adders considering over a dozen activity scenarios of input vector changes. Based on extended power model of static CMOS gates accurate analysis is done, thanks to the fact, that the model take into consideration changes of input vectors, not only switching activity of signals. Various structures of PG tree have been examined: regular, non-regular, with grey cells only, with both grey and black and with higher valency cells. Obtained results shows that some structures are better for some kind of summed data, but general remarks for adders design can be derived.