Design of Dual-Channel AIS Digital Receiver

Abstract

A design of dual-channel digital AIS (Automatic Identification System) receiver based on FPGA is introduced. This innovation of this paper is dividing into two channels by mixer, decimation and filter. The Channelization", "mixer, FIR filter, FM decoder and GMSK decoder digitized will simplify the design of analog circuits and improve the stability and reliability of the equipment. The theoretical and hardware programs of the system are described. The main theories and modules in FPGA are described in detail. The correctness of program is proved by experiment.