Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience

Abstract

The traditional test model of go/no-go testing being questioned by increasing delay fault manifestations has become even further challenged as a result of unpredictable soft errors. Consequent probabilistic fault manifestations shift the focus to fault resilience mechanisms and tradeoffs of false alarms vs. escapes. Fault manifestation at flip-flops necessitates solutions that rely on their hardening, possibly imposing inordinate cost as flip-flops constitute a significant fraction of current designs. A two-pronged approach for resolving this challenge is necessitated, consisting of frugal flip-flop designs, capable of withstanding such faults, and an economic rationalization model to enable a prioritized flip-flop selection within an overall design budget. In this paper, we propose a hardened flip-flop that increases circuit tolerance to soft errors and delay faults simultaneously and the associated selective hardening scheme guided by a unified quality evaluation framework. The proposed flip-flop supersedes previous research efforts and simulation results show that the outlined framework delivers yield recovery and FIT reduction at a minimized hardware cost.