A 97.6%-Efficient 1-2MHz Hysteretic Buck Converter with 7V/μs DVS-Rate Enabled by Isosceles-Triangular Shunt Current Push-Pull Technique

H. Bae, Jeong-Hyun Cho, Gyeong-Gu Kang, Yousung Park, Hyunsik Kim
{"title":"A 97.6%-Efficient 1-2MHz Hysteretic Buck Converter with 7V/μs DVS-Rate Enabled by Isosceles-Triangular Shunt Current Push-Pull Technique","authors":"H. Bae, Jeong-Hyun Cho, Gyeong-Gu Kang, Yousung Park, Hyunsik Kim","doi":"10.1109/vlsitechnologyandcir46769.2022.9830181","DOIUrl":null,"url":null,"abstract":"This paper presents a fast dynamic voltage scaling (DVS) buck converter without losing high efficiency. The proposed isosceles-triangular shunt current (ITSC) push-pull technique allows a turning-point for optimal DVS to be independent of passive components while supplying sufficient current of 35A/μs. Current-tailing handover (CTH) realizes no voltage droop after DVS even under resistive loads. ITSC and CTH can also enhance load-transient response. The chip fabricated in 180-nm CMOS achieves 7V/μs DVS-rate and 97.6% peak efficiency.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830181","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

This paper presents a fast dynamic voltage scaling (DVS) buck converter without losing high efficiency. The proposed isosceles-triangular shunt current (ITSC) push-pull technique allows a turning-point for optimal DVS to be independent of passive components while supplying sufficient current of 35A/μs. Current-tailing handover (CTH) realizes no voltage droop after DVS even under resistive loads. ITSC and CTH can also enhance load-transient response. The chip fabricated in 180-nm CMOS achieves 7V/μs DVS-rate and 97.6% peak efficiency.
采用等腰三角形分流电流推挽技术实现7V/μs dvs速率的97.6%效率1-2MHz滞回降压变换器
提出了一种不损失高效率的快速动态电压缩放降压变换器。提出的等腰三角形分流电流(ITSC)推挽技术允许最佳DVS的转折点独立于无源元件,同时提供35A/μs的足够电流。电流尾切换(CTH)即使在电阻性负载下,也能实现无电压下降。ITSC和CTH也可以增强载荷的瞬态响应。该芯片采用180nm CMOS工艺,实现了7V/μs的dvs速率和97.6%的峰值效率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信