Threshold voltage in tunnel FETs: physical definition, extraction, scaling and impact on IC design

Abstract

This work reports on the physical definition and extraction of threshold voltage in tunnel FETs based on numerical simulation data. It is shown that the tunnel FET has the outstanding property of having two threshold voltages: one in terms of gate voltage, V_TG, and one in terms of drain voltage, V_TD. These threshold voltages can be physically defined based on the saturation of the barrier width narrowing with respect to V_G or V_D. The extractions of V_TG and V_TD are performed based on the transconductance change method in the double gate tunnel FET with a high-k dielectric, and a systematic comparison with the constant current method is reported. The effect of gate length scaling on these threshold voltages, current, conductance characteristics, g_m/I_D and g_m/g_ds of the tunnel FET is investigated for the first time.