JABR 265

Abstract

The design for the JABR 265 8-bit minicomputer was done as part of the coursework for a class at the University of Illinois. The class was Computer Science 265, a logic design laboratory taught by Professor M. Faiman. The processor was designed to be built with the U of I's 'Excel' logic design boxes. There are three main principals or 'themes' upon which the design of this processor is based: (1) Memory is paged, (2) the CPU contains a register file, and (3) the processor is microprogrammed. The decision to use a paging scheme for addressing is based on the simple fact that 8 bits provide an extremely limited addressing capability. The use of a register 'file' made the implementation of the 3rd 'theme' simpler since 'spare' registers were used for scratchpads and there were still plenty of registers for both dedicated user and CPU usage. By designing the processor as a microprogrammed machine, the actual hardware implementation was simplified.