Wafer Reliability Evaluation and Monitoring for InGaAsP Devices

Abstract

A simple procedure, evaluating wafer reliability by HALT before full regular processing, is justified and optimized. This procedure is aimed at early failure rate assessment, reliability adjustment, and yield enhancement per customer needs. A test plan concept, detailed design and realization are suggested. Test optimization with respect to customer requirements, field failures, and manufacturing losses are presented. Some regular flaws and recommendations are proposed. The procedure allows significant manufacturing and field savings along with increasing customer satisfaction. The procedure can be extended to manufacturing operation optimization and applied to related GaAs and Si based innovative technologies