D. Murray, J. Burnette, Brian Campbell, M. Chung, Bruce Fernandes, S. Ghosh, Rajat Goel, G. Hess, Hang Huang, Zhibin Huang, Naveen Javarappa, Pradeep Kanapathipillai, F. Klass, F. Liu, A. Mehta, Y. Modukuru, Nishant Nerurkar, Abhijit Radhakrishnan, S. Santhanam, J. Sugisawa, Shyam Sundar, Honkai John Tam, R. Wen, E. Wu, Jung-Cheng Yeh, J. Yong, S. Zambare
{"title":"A 2GHz, 7W (max) 64b PowerTM Microprocessor Core","authors":"D. Murray, J. Burnette, Brian Campbell, M. Chung, Bruce Fernandes, S. Ghosh, Rajat Goel, G. Hess, Hang Huang, Zhibin Huang, Naveen Javarappa, Pradeep Kanapathipillai, F. Klass, F. Liu, A. Mehta, Y. Modukuru, Nishant Nerurkar, Abhijit Radhakrishnan, S. Santhanam, J. Sugisawa, Shyam Sundar, Honkai John Tam, R. Wen, E. Wu, Jung-Cheng Yeh, J. Yong, S. Zambare","doi":"10.1109/CICC.2007.4405833","DOIUrl":null,"url":null,"abstract":"The PA6T core is an out-of-order superscalar implementation of the power architecture. Power efficiency is achieved through micro-architecture, logic, and circuit optimizations. The processor is fabricated in a 65 nm, triple Vt, dual oxide 8 M CMOS process. Worst-case power dissipation at 2 GHz is 7 W.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2007.4405833","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The PA6T core is an out-of-order superscalar implementation of the power architecture. Power efficiency is achieved through micro-architecture, logic, and circuit optimizations. The processor is fabricated in a 65 nm, triple Vt, dual oxide 8 M CMOS process. Worst-case power dissipation at 2 GHz is 7 W.
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