An Efficient PCS to Transmit FEC-coded Frames in Ethernet PON

Abstract

A method to efficiently transmit FEC-coded frames in PCS for Ethernet PON is proposed. Comparing with IEEE 802.3ah Clause 65.2.3, the proposed architecture requires only one 8b/10b encoder and is IEEE 802.3ah-compliant. This method speeds up the circuit and reduces the gate counts. In StratixII EP2S180 FPGA, the proposed method, comparing with the standard, saves 40.7% ALUs and increases 18% speed. Using TSMC013LP technology, our method saves 29% gate counts, and increases 26% speed. Additionally, the proposed method can be easily concatenated after the ordinary Ethernet TRANSMIT process with the removal of the 8b/10b encoder.