A marvelous low on-resistance 20V rated self alignment trench MOSFET (SAT-MOS) in a 0.35/spl mu/m LSI design rule with both high forward blocking voltage yield and large current capability

Abstract

In this paper, we propose the SAT-MOS, which achieved marvelous performance of the specific on-resistance (Ron, sp): 6.5 m/spl Omega/mm/sup 2/ (@Vdss=30.8 V) by minimizing the unit cell pitch on a 0.35 /spl mu/m LSI design rule. This is the lowest value of 20 V rated MOSFETs ever been reported. The fabricated SAT-MOS Ron,sp ratio to the Si limit reaches the ultimate value of 208% in this voltage class. The SAT-MOS maintains an excellent Vdss uniformity on a wafer, because our proposed SAC (shallow trench contact) structure and procedure has a very large process window for SAC trench depth if the source contact trench depth disperses more than 20%. As a result, we could present the SAT-MOS, which has both a large current capability of over 100 A/mm/sup 2/ in a static forward bias condition and an avalanche ruggedness of over 25 A/mm/sup 2/ during unclamped inductive switching (UIS).