A gain-compensated switched capacitor integrator

Abstract

A topology of switched capacitor integrator with gain compensation is proposed. It employs the same input as in the integrating phase during the calibration cycle to compensate for the integrating pole error due to the finite gain of the op-amp, and it eliminates the need of a "slow motion input" requirement. The proposed topology can be used, for example, in the switched capacitor implementation of sigma-delta modulators.