Data level parallel processing for object recognition on Recursive Torus Architecture

Abstract

The paper gives a brief overview of the hardware design of RTA/1 (with 1024 PEs), a parallel machine designed based on the Recursive Torus Architecture (T. Matsuyama et al., 1993). We developed a small scale prototype machine with 16 PEs, RTA/0, to evaluate its performance. Then, we propose a scheme of data level parallel processing on RTA/1 and demonstrate its utilities by implementing complex parallel processes for bottom up object recognition on RTA/0.