Modeling analog chips as if they are digital

Abstract

While generating Test Program Sets (TPS) for HYBRID electronic boards, test engineers can choose from: 1. Generating analog tests by ATLAS or a similar language for the analog part of the Unit Under Test (UUT) and generating digital tests by LASAR for the digital part of the UUT. 2. Generating a single test by ATLAS for both the analog and the digital parts of the UUT. This paper presents another method to generate a single LASAR test that covers both analog and digital components of the OUT. With this method the analog components of the UUT are treated as if they are digital. After the testing strategy is set, behavioral, functional and structural models of the analog chips can be simulated by LASAR. During test generation, treating the whole unit as a digital board will reduce the complexity of the test strategy, the test generation time and consequently the cost of the TPS. The work presented by this paper is based on real-world experience. Real-world examples involved in this paper demonstrate the practicality and the applicability of the method.