Feature Selection for Cost Reduction In MCU Performance Screening

Abstract

In safety-critical applications, microcontrollers must satisfy strict quality constraints and performances in terms of $F_{\max}$, that is, the maximum operating frequency. It has been demonstrated that data extracted from on-chip ring oscillators, the so-called speed monitors, can model the $F_{\max}$ of integrated circuits using machine learning models. Those models are suitable for the performance screening process, and they use speed monitors are features, while the target is the Fmax. But if the number of features used for building a machine learning model is huge, the risk of over-fitting or curse of dimensionality is high, leading to a high generalization error. Also, devices with a high number of ring-oscillator are costly to be produced. This paper copes with supervised feature selection in microcontroller performance screening during the early phase of prototyping and presents methodologies to reduce the number of monitors needed to build efficient machine learning models without losing in accuracy. We propose a methodology to rank features according to their importance in the performance prediction, able to extract a subset of them drastically reduced in size, but still able to well solve the underlying task. Experiments showed that the chosen subset of features leads to simpler ML models that can achieve lower prediction error, reducing overfitting. This permits avoiding inserting the full set of sensors in the final product, with a huge saving of money and physical space in the silicon.