An integrated 9-channel time digitizer with 30 ps resolution

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.993038

A. Mantyniemi, T. Rahkonen, J. Kostamovaara

引用次数: 60

Abstract

An integrated 9-channel time digitizer with 30 ps RMS resolution, 496 /spl mu/s range, and 50 mW power consumption in 0.6 /spl mu/m CMOS uses a three-stage delay line interpolation and delay-generation principle that divides the 66 MHz clock period into 512 bins using only 45 delay elements.

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集成9通道时间数字化仪，分辨率30ps

集成的9通道时间数字化仪具有30 ps RMS分辨率，496 /spl mu/s范围和50 mW功耗，0.6 /spl mu/m CMOS，采用三级延迟线插值和延迟产生原理，仅使用45个延迟元件将66 MHz时钟周期划分为512个桶。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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