Evolving hierarchical low disruption fault tolerance strategies for a novel programmable device

Abstract

Faults can occur in transistor circuits at any time, and increasingly so as fabrication processes continue to shrink. This paper describes the use of evolution in creating fault recovery strategies for use on the PAnDA architecture. Previous work has shown how such strategies, applied in a random but biased fashion can be used to overcome transistor faults and also how, without knowledge of the fault, the average time to find a fix could be reduced. This work presents a further optimisation where an Evolutionary Algorithm (EA) is used to optimise the order that deterministic strategies are applied to a faulty circuit in order to reduce the average time to find a fix. The two methods are compared and this comparison is used to set the path for future work.