A systematic generation of fault tolerant systolic arrays based on multiplicated multiple modular redundancy

Abstract

A systematic procedure to configure fault-tolerant systolic arrays based on Multiplicated Multiple Modular Redundancy is proposed. Resultant systolic arrays tolerate failures not only on processing elements but also on communication links. While, to guarantee the fault-tolerance on communication links, sophisticated connection schemes between processing elements are needed in general, link complexity is reduced by optimizing the redundant operation scheme.