A 16b 5MSPS two-stage pipeline ADC with self-calibrated technology

Abstract

The accuracy limitation of analog-to-digital converters (ADCs) is mainly set by component mismatches and amplifier offsets. A new two-stage architecture ADC is presented and some of the issues of digital calibrate technique are discussed. The design of ADC uses a modified pipeline technique based on Successive-Approximation ADCs. The proposed architecture does not need an auxiliary DAC for reconstruction at each stage. Rather than achieving high precision by adjustment of analogy component values, we present a native digital technique to calibrate pipeline ADC, which calibrates linearity and gain with the same hardware. In digital calibration operations, the overlap condition will occur in edge of the full-scale voltage inevitably. Here we design a simple circuit which uses one adder to implement the over-or underrange protection. In order to get bipolar mode, the converter using dual-voltage suppliers (±5V) is required. The circuit was designed in the P-well HVCMOS process. The experiments results are presented to show the effectiveness of the design method and the precision of the analog-to-digital conversion is up to16-bit.