Soft error detection via double execution with hardware assistance

Abstract

As technology trends keep pushing cell dimensions in semiconductors to smaller geometries and higher densities, modern digital systems are increasingly becoming more vulnerable to reliability issues originated by soft errors. Various techniques used to detect soft errors are accomplished by incorporating redundancy into the hardware or software, but the penalty associated with the added redundancy can be measured by the high cost of the extra hardware or the degradation in performance for software-added redundancy. We are proposing a technique that compromise between hardware and software redundancy approaches. This approach is based on a software time redundancy combined with some hardware assistance. This hybrid technique has the potential to improve performance by adding a limited amount of hardware assistance when compared with a common time redundancy approach. It is also designed to set a foundation for further investigation into variations of this technique to improve soft error detection with better performance and less hardware.