Parallel packet forwarding architecture using ATM switch core for scalable performance

Abstract

This paper proposes a label switch router architecture using ATM switch core. Hardware-based forwarding engines are attached to the switch core in a scalable fashion in the proposed label switch router. Dimensioning the number of forwarding engines is proposed to achieve scalable performance. An ATM virtual circuit is used as label switched path in the MPLS network. Traffic management and OAM capabilities are applied to achieve carrier-grade network control for the network infrastructure the next generation Internet is to provide.