Early system analysis of cache performance for RISC systems

Abstract

The implications of packaging and interconnection technologies for reduced instruction set computing (RISC) microprocessor memory hierarchies are examined. Prior early analysis tools have taken either cache performance or interconnection models into consideration. Here such analyses are combined and extended to be more specific to RISC microprocessor cache systems. The resulting first-order model allows interactive investigation of tradeoffs at prenetlist phases of design. After summarizing the model, several test cases are presented which illustrate trends and begin to quantify design tradeoffs.<>