Design and Analysis of High Speed Dynamic Comparator for Area Minimization

Abstract

Comparators are basic building block for analog to digital converter (A/D converter) as well as many mixed signal processing circuits. Therefore, it is very essential to improve its power dissipation and speed, keeping the chip area as compact as possible due to the increasing demand of portable devices. This paper discusses, a modified latched comparator and its characteristics are compared with the conventional models from different literature. The proposed circuit is simulated using Spectre Circuit Simulator tool-Cadence. The target is to achieve low power consumption with low delay profile in a lowest possible chip area. Feature size is considered to be 90nm. Power and delay are measured and compared with other comparators that were proposed earlier for representing the improvement of proposed model. Its power dissipation is 33.5 μw and delay is 54.32ps. The chip area is found to be (8.83*8.61) μm2. Also, it has low parasitic effect and low noise in comparison with those conventional models.