IIR digital filter for delta-sigma decimation, channel selection, and square-root raised-cosine nyquist filtering

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992970

S. Mirabbasi, K. Martin

引用次数: 4

Abstract

A 1.8 V 0.18 /spl mu/m CMOS /spl Delta//spl Sigma/ decimation filter also performs channel-selection and an approximate root-raised-cosine Nyquist pulse-shaping. The 0.1 mm/sup 2/ IIR structure consumes 6.4 mW (26.8 mW) at 64 MHz (240 MHz) oversampling frequency.

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IIR数字滤波器用于delta-sigma抽取，通道选择和平方根提高余弦奈奎斯特滤波

一个1.8 V 0.18 /spl mu/m CMOS /spl Delta//spl Sigma/抽取滤波器也执行通道选择和近似的根提升余弦奈奎斯特脉冲整形。0.1 mm/sup 2/ IIR结构在64 MHz (240 MHz)过采样频率下消耗6.4 mW (26.8 mW)功率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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