High Throughput Architecture for KLEIN Block Cipher in FPGA

Abstract

In recent times, lightweight cryptographic algorithms have drawn a lot of attention to the researchers for securing the fast and small-computing devices. However, different algorithms have been developed to fulfill the requirements, and there has not been much research on transforming these algorithms to Field Programmable Gate Arrays (FPGAs) with minimal optimization. These reprogrammable devices are highly attractive options for hardware implementations of encryption algorithms. A strong focus is placed on high-throughput implementations, which are required to support security for current and future high bandwidth applications. In this paper, two different architectures are designed for resource-constrained environments. Among them, parallel processing implementation achieves high throughput of 2070.39 and 1646.12 Mbps on xc5vlx50t-3ff1136 and xc4vlx25-12ff668 devices, respectively. While in the other design, 8-bits datapath architecture signifies the use for low I/O port devices. All results are simulated and verified for different devices of Xilinx Spartan & Virtex families.