18.1 A -105dBc THD+N (-114dBc HD2) at 2.8VPP Swing and 120dB DR Audio Decoder with Sample-and-Hold Noise Filtering and Poly Resistor Linearization Schemes

Abstract

Three major design issues that arise for high-fidelity audio decoders are: 1) DAC reference noise limiting achievable SNR [1], [2]; 2) THD+N degradation at large output swing [3], [4]; and 3) Distortion arising from limited amplifier loop gain as a consequence of high output load capacitance (CL) [5]. In the first issue, reference noise along with individual DAC cell noise generally limits SNR for a full-scale signal. The use of large device sizes [1], source degeneration [2] and chopping can mitigate 1/f noise, but none are effective for reducing thermal noise. Consequently, either more power or an external bypass capacitor for noise filtering is necessary for reducing DAC reference noise. In the second issue, THD+N of high-output-swing amplifiers degrades proportionally as the output swing increases above 1.6VPP, even with a 4.5V supply [3], [4]. The primary cause of this severe 2nd-order harmonic distortion (HD2) is due to the depletion effect of poly resistors [6]. Lastly, for adequate stability margin, the UGB and loop gain of the conventional nested Miller compensation (NMC) amplifier is restricted by an output limiting pole $(\omega _{\mathrm{limit}})$ and CL. In [5], a frequency compensation scheme is proposed to push the UGB close to $\omega _{\mathrm{limit}}$ and enhance the loop gain over the audio band (20Hz to 20kHz) while handling a CL up to 10nF. However, with a CL of 22nF, the amplifier begins to ring for a transient step. In this work, three solutions are presented to solve the aforementioned issues: 1) an area- and power-efficient sample-and-hold (S&H) noise filtering technique is introduced to shape the 1/f and thermal noise of the reference to frequencies below the audio band, thus greatly improving SNR for a full-scale signal; 2) a poly resistor linearization scheme is presented to improve HD2 by mitigating the depletion effect of resistors; and 3) a frequency compensation method for multistage amplifiers is introduced that boosts loop gain and thus enhances amplifier linearity without being limited by large CL. Combining these techniques, the decoder and amplifier achieve -105dBc THD+N (-114dBc HD2) and 120dB DR, and can support a CL up to 22nF.