Mixing fixed and reconfigurable logic for array processing

Abstract

This paper describes the architecture of the MIX system that was designed to investigate the trade-off between the use of reconfigurable and fixed logic. The calculation of the dot-product of two vectors of 32 bit floating point numbers, that forms the basis of array processing in many engineering applications, is used as the basic algorithm for the investigation. The results indicate that fixed logic is more suited for floating point units and memories while reconfigurable logic is useful for implementing control logic providing significant flexibility. It was also found that the additional delay in reconfigurable logic can effectively overlap with the operating time of the fixed logic subsystems. The advantage of reconfigurability of the control is therefore combined with the high bandwidth properties of the fixed logic.