Latency insertion method (LIM) for CMOS circuit simulations with multi-rate considerations

Abstract

In this paper, we present an application of the latency insertion method (LIM) to the transient simulations of CMOS circuits and compare it to traditional SPICE based methods. In addition, we extend the multi-rate simulation technique and apply it to the simulation of CMOS circuits in the LIM environment and illustrate its computational efficiently over the basic LIM.