Zero-skew-clock algorithms for high performance system on a chip

Abstract

The high performance circuit design has become an essential trend for system-on-a-chip (SoC). Hence, physical design automation is getting more and more complex due to parasitic effects, especially wire delay. We propose a new flexible clock distribution network design to approach solving the clock skew problem and supporting "plug-and-play" in SoC integrated overall SoC operation. The algorithm based on clock skew without changing interconnect signal and it can be easily implemented for SoC design flow. The design turn around times can be greatly reduced.