J.M. Duffalo, S. Domer, R. Hollstein, A.K. Hullinger, A. Niederkorn, N.J. Wecker
{"title":"A scalable thermal mechanical test chip for package characterization and qualifications","authors":"J.M. Duffalo, S. Domer, R. Hollstein, A.K. Hullinger, A. Niederkorn, N.J. Wecker","doi":"10.1109/IRWS.1994.515825","DOIUrl":null,"url":null,"abstract":"A thermal mechanical test chip (TMTC) has been designed to reduce the cycle time and cost of package reliability qualifications. The TMTC moves package reliability assessment closer to the package and assembly development cycle by breaking the tie between silicon qualification and package qualification. This approach comprehensively addresses both the mechanical and the thermal reliability issues of package assembly without the added design and manufacturing costs of a full flow silicon test chip.","PeriodicalId":164872,"journal":{"name":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRWS.1994.515825","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A thermal mechanical test chip (TMTC) has been designed to reduce the cycle time and cost of package reliability qualifications. The TMTC moves package reliability assessment closer to the package and assembly development cycle by breaking the tie between silicon qualification and package qualification. This approach comprehensively addresses both the mechanical and the thermal reliability issues of package assembly without the added design and manufacturing costs of a full flow silicon test chip.