{"title":"An Improved SJ UMOS with Modified Gate Electrode to Reduce Gate Charge","authors":"Prashant Kushwaha, Payal Nautiyal, Anshul Gupta, Alok Naugarhiya, Shrish Verma","doi":"10.1109/IEMECONX.2019.8877004","DOIUrl":null,"url":null,"abstract":"An improved superjunction (SJ) device structure with modified gate electrode has been proposed in this paper. The trench gate has been altered to reduce gate capacitance associated with drain (CGD). Lesser is the CGD, better is the switching performance. The structural modification is optimized to obtain minimum CGD without degrading any other performance parameter. The SJ device considered in this paper has maximum operating voltage of around 680 V. Simulation results demonstrates 44.8% improvement in gate to drain charge of proposed device implying better Figure of merit.","PeriodicalId":358845,"journal":{"name":"2019 9th Annual Information Technology, Electromechanical Engineering and Microelectronics Conference (IEMECON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 9th Annual Information Technology, Electromechanical Engineering and Microelectronics Conference (IEMECON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMECONX.2019.8877004","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
An improved superjunction (SJ) device structure with modified gate electrode has been proposed in this paper. The trench gate has been altered to reduce gate capacitance associated with drain (CGD). Lesser is the CGD, better is the switching performance. The structural modification is optimized to obtain minimum CGD without degrading any other performance parameter. The SJ device considered in this paper has maximum operating voltage of around 680 V. Simulation results demonstrates 44.8% improvement in gate to drain charge of proposed device implying better Figure of merit.