An Improved SJ UMOS with Modified Gate Electrode to Reduce Gate Charge

Prashant Kushwaha, Payal Nautiyal, Anshul Gupta, Alok Naugarhiya, Shrish Verma
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引用次数: 1

Abstract

An improved superjunction (SJ) device structure with modified gate electrode has been proposed in this paper. The trench gate has been altered to reduce gate capacitance associated with drain (CGD). Lesser is the CGD, better is the switching performance. The structural modification is optimized to obtain minimum CGD without degrading any other performance parameter. The SJ device considered in this paper has maximum operating voltage of around 680 V. Simulation results demonstrates 44.8% improvement in gate to drain charge of proposed device implying better Figure of merit.
一种改进的SJ型UMOS及其栅极修饰以降低栅极电荷
本文提出了一种改良的栅极超结(SJ)器件结构。沟槽栅极被改变以减少与漏极(CGD)相关的栅极电容。CGD越小,开关性能越好。在不降低任何其他性能参数的情况下,优化结构修改以获得最小的CGD。本文所考虑的SJ器件的最大工作电压约为680 V。仿真结果表明,该器件栅极漏极电荷改善44.8%,具有更好的性能图。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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