An Area Efficient and Inductorless Implementation of Continuous-Time Linear Equalization Scheme for High Speed and Low Noise TIA Designs

Abstract

This paper presents an inductorless fully differential and linear design of continuous time linear equalization (CTLE) to simultaneously optimize the bandwidth and noise of transimpedance amplifiers. The proposed CTLE is implemented with RC components in a negative feedback configuration. The proposed design is compared with the conventional CTLE approach that uses an inductor-based implementation. The comparison suggests that the proposed CTLE not only achieves the same equalized bandwidth but also results in less group delay variations as compared to its inductor-based counterpart. Additionally, a TIA is designed using the proposed CTLE approach in GF-BiCMOS 90 nm $(\mathbf{f}_{\mathrm{t}}=\boldsymbol{310}$ GHz) process and its performance is verified by post-layout simulations which include the loading effects of photodiode and $50-\Omega$ output loads. As per the authors' best knowledge, the proposed TIA design is the first of its kind in the sense that without the use of inductors in any stage, it can support up to 80 Gb/s NRZ data stream with a transimpedance gain of 72 $\mathbf{dB}-\Omega$ and an input-referred noise density of about 1.25 pA/sqrt(Hz).