Test vector compression via statistical coding and dynamic compaction

Abstract

This paper addresses the problem of increasingly longer test times and greater test data storage requirements for integrated circuits. A new compression/decompression technique is proposed for reducing the amount of data that must be stored on the tester and transferred to the chip. This technique uses static and dynamic compaction algorithms in conjunction with statistical coding to encode test vectors provided by circuit vendors. The decoding process is performed in hardware by a small amount of on-chip circuitry. Taken together, this compression/decompression algorithm results in both lowered tester storage requirements and reduced test times.