A 0.3-to-8.5GHz frequency synthesizer based on digital period synthesis

Tapio Rapinoja, K. Stadius, J. Ryynänen
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引用次数: 1

Abstract

This paper presents a wide-band digital frequency synthesizer based on digital period synthesis (DPS). As a direct frequency synthesis method, the DPS architecture achieves inherently wide operational band, high frequency resolution and instantaneous settling. The frequency synthesizer, including reference delay-locked loop (DLL), DPS unit, and frequency multiplying DLL, was implemented in a 65-nm CMOS process and it occupies an active area of 0.3 mm2. The implemented frequency synthesizer covers a frequency range from 0.3 GHz to 8.5 GHz with 1 Hz frequency resolution, 550 fs integrated jitter, and 0.9 μs settling time.
一种基于数字周期合成的0.3 ~ 8.5 ghz频率合成器
提出了一种基于数字周期合成(DPS)的宽带数字频率合成器。DPS结构作为一种直接频率合成方法,具有固有的宽工作频带、高频率分辨率和瞬时沉降等优点。频率合成器包括参考锁延环(DLL)、DPS单元和倍频DLL,采用65纳米CMOS工艺实现,其有效面积为0.3 mm2。所实现的频率合成器覆盖0.3 GHz至8.5 GHz的频率范围,频率分辨率为1 Hz,集成抖动为550 fs,沉降时间为0.9 μs。
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