Overcoming bottlenecks in high-speed transport systems

Abstract

An architecture is presented for HSLAN/MAN controllers. This front-end processor system (FEP) is designed for operation in a CLN/LLC 1 environment, and implements the ISO OSI TP4 transport protocol. The FEP uses one or more commercial microprocessors with layers 2b-4 implemented in firmware. The protocol processors are supported by custom VLSI hardware such as a checksummer, DMA units, and process coupling devices as required. Layers 1 and 2a are provided by commercial chipsets. The FEP is optimised for a LAN/MAN environment while allowing the host to communicate over wide-area networks. It is general enough to be adapted to non-OSI protocol suites. Initial estimates indicate that the FEP should be able to transmit and receive at full FDDI bandwidth with a TPDU length of 1k octets.<>