Networks-on-Chip: Challenges, trends and mechanisms for enhancements

Abstract

The rate of increase of silicon capacity in Integrated Circuits (IC) will enable system integration of several billion transistors to reside on a single chip in the near future. Future System-on-Chip (SoC) systems must therefore integrate upto several hundreds of cores within a single chip, and SoC designs will employ on-chip communication networks (NoCs) as a result. This paper discusses the problems with many current SoC systems, surveys the challenges and trends facing future SoC designs and proposes a mechanism for enhancing NoC strategies of the future by enhancing memory management and utilization techniques within an NoC.