Backend process optimization for 90 nm high-density ASIC chips

Abstract

Based on the marketing, methodology, and manufacturing requirements of ASIC products, an optimum back-end process for high-density ASIC chips in a 90 nm technology is proposed. The chip size for high-density ASIC chips has stayed roughly constant between 7 and 14 mm on a side. High-density chips are achieved with tight pitch for all routing levels. Optimum performance is obtained with a thinner metal 2 and 3 Cu thickness of 0.25 versus 0.35 /spl mu/m for the higher levels of metal.