Digit-serial VLSI microarchitecture

Abstract

The authors illustrate the techniques by which a simple function library may be widely parameterized to meet the diverse function, throughput and accuracy requirements in high-performance integer arithmetic applications. In a design automation environment the user's view of these structures is, in the case of multipliers and adders, a simple functional icon carrying synthetic parameters which are derived from global throughput and accuracy requirements. Shifters are included automatically for consistency, allowing usage of the specified numerical resources to be maximized for any application. Processors of throughputs approaching one billion operations/sec may be easily assembled using these techniques, figures which are difficult to achieve in conventional architectures. The full power of parallelism and pipelining is brought to bear on computational problems, the price paid being the loss of inherent programmability.<>