Towards the empirical design of massively parallel arrays for spatially mapped applications

Abstract

Although SIMD arrays have been built since the 1960's, they have undergone few empirical studies. The underlying problems-which have included the lack of a unified architectural framework and the computational intractability of simulating large PE arrays-are addressed through the use of trace compilation, a novel approach to trace driven simulation. The results indicate the benefits of adding another level to current SIMD array memory designs. Also, surprising results were obtained about performance effects of varying cache associativity and block size. Together, they indicate that while SIMD array programs have sufficient locality to make PE caches worthwhile, the type of locality may differ fundamentally from that of serial machine and multiprocessor programs. Other results demonstrate the limitations of increasing the datapath width and inter PE communication bandwidth without corresponding improvements in other processor features.