Tamer Dallou, D. C. S. Lucas, G. Araújo, Lucas Morais, Eduardo Ferreira Barbosa, Michael Frank, Richard Bagley, Raj Sayana
{"title":"Task parallel programming model + hardware acceleration = performance advantage","authors":"Tamer Dallou, D. C. S. Lucas, G. Araújo, Lucas Morais, Eduardo Ferreira Barbosa, Michael Frank, Richard Bagley, Raj Sayana","doi":"10.1109/HOTCHIPS.2016.7936235","DOIUrl":null,"url":null,"abstract":"This article consists only of a collection of slides from the author's conference presentation.","PeriodicalId":363333,"journal":{"name":"2016 IEEE Hot Chips 28 Symposium (HCS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Hot Chips 28 Symposium (HCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTCHIPS.2016.7936235","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This article consists only of a collection of slides from the author's conference presentation.
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